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VHDL QUESTIONS

VHDL for 2to1 Multiplexer
VHDL for 2to1 Multiplexer
To fix the issue you can do This is what I'm trying to write in VHDL code: , Multiplexer :
TAG : vhdl
Date : October 21 2020, 06:10 PM , By : Jonathan Turla
VHDL: convert "real" and "time" variables into strings for display on console
VHDL: convert "real" and "time" variables into strings for display on console
Hope that helps This is easy, a type's image attribute is a function that convert that type to a string representation:
TAG : vhdl
Date : October 16 2020, 06:10 AM , By : Claudio Luna
need VHDL equivalent of c-language "strtok" and "strcmp" functions that can operator on vhdl string
need VHDL equivalent of c-language "strtok" and "strcmp" functions that can operator on vhdl string
With these it helps I'm trying to write a stimulus reader for vhdl testbench. it needs to read a text command and two text operands delimited by whitespaces in a text file.
TAG : vhdl
Date : October 14 2020, 06:10 PM , By : Z.ghizlane
in VHDL, how to check if file exists before opening it?
in VHDL, how to check if file exists before opening it?
around this issue In Verilog, I can check if a file exists by opening the file and then checking if the file descriptor is zero, and if it is not to assume the file doesn't exist. For example, as follows: , When you open a file, for example:
TAG : vhdl
Date : October 13 2020, 12:00 AM , By : Donald Shaw
VHDL: including file type inside of a VHDL Record structure?
VHDL: including file type inside of a VHDL Record structure?
around this issue When I have tried to remove file in your code, I got this error :
TAG : vhdl
Date : October 12 2020, 11:00 AM , By : Mathieu Flamand
GHDL simulator doesn't support vhdl attributes without error?
GHDL simulator doesn't support vhdl attributes without error?
should help you out See IEEE Std 1076-2008 7.2 Attribute specification, paragraph 9:
TAG : vhdl
Date : October 12 2020, 09:00 AM , By : Carlos
For Verilog/VHDL simulation: how to open modelsim wlf file from command line?
For Verilog/VHDL simulation: how to open modelsim wlf file from command line?
around this issue With GtkWave I can simply open a vcd waveform file from the command line as follows: , You're looking for the -view option of modelsim:
TAG : vhdl
Date : October 12 2020, 03:00 AM , By : Turlacu Andrei Viore
What's the VHDL equivalent of verilog 2001's “+:” operator?
What's the VHDL equivalent of verilog 2001's “+:” operator?
I think the issue was by ths following , This seems to be a bit of an XY Problem. The Verilog :+ (or -:) operator is a bit of a hack to get round the fact that this kind of thing:
TAG : vhdl
Date : October 10 2020, 03:00 AM , By : Ram
in VHDL, is it possible to create an array of std_logic_vector without using a type?
in VHDL, is it possible to create an array of std_logic_vector without using a type?
it fixes the issue What you created is an array of an array - which is in general what you want. What @Matthew Taylor created is a multidimensional array. WIth VHDL-2008 the elements of a composite can be unconstrained, and hence, you can create:
TAG : vhdl
Date : October 10 2020, 12:00 AM , By : Jim ODonnell
operation of std_logic:='X'
operation of std_logic:='X'
wish helps you The type std_logic is an enumeration type with 9 values and has the following 9 values:
TAG : vhdl
Date : October 09 2020, 03:00 AM , By : TheITGUI
In VHDL-2008, how to format "real" similar to "%f" in c-language, example: sprintf(str, "%9.6f&
In VHDL-2008, how to format "real" similar to "%f" in c-language, example: sprintf(str, "%9.6f&
To fix the issue you can do I'm using VHDL-2008 and I want to nicely format real numbers are strings similar to this c-language function: , VHDL 2008 provides to_string for real in 3 flavours:
TAG : vhdl
Date : October 07 2020, 09:00 PM , By : Vũ Nguyễn
Latch data when differs from zeros
Latch data when differs from zeros
wish helps you This looks like a delta race condition where NotZero and Data are both dependent on inData, but Data is also dependent on NotZero = '1'. NotZero changes to '0' in the current delta cycle, but the Data expression has not seen this updat
TAG : vhdl
Date : October 07 2020, 08:00 AM , By : Bart
How to emulating C++ classes in VHDL-2008 or above
How to emulating C++ classes in VHDL-2008 or above
may help you . Is there a way to emulate the data encapsulation features of a C++ class in VHDL-2008 using just VHDL functions and VHDL records? I've seen this type of thing done many times in languages such as "c", but very rarely for VHDL. , What I
TAG : vhdl
Date : October 07 2020, 08:00 AM , By : James Crowley
VHDL: bound check error when adding two numbers
VHDL: bound check error when adding two numbers
it should still fix some issue The vector operand of the addition should have the same length as the target of the assignment. Extend if needed:
TAG : vhdl
Date : October 06 2020, 03:00 PM , By : Alan Wooley
VHDL: setting a constant conditionally based on another constant's value
VHDL: setting a constant conditionally based on another constant's value
hope this fix your issue I need to set a constant's value using an "if-else" or "case", and select a different constant value based on another constant's value. Is this possible in VHDL? It would be a one time change of constant values at the beginni
TAG : vhdl
Date : October 06 2020, 07:00 AM , By : shiliang
image rom display VGA
image rom display VGA
hop of those help? i am doing code using VHDL FPGA the code content 3 part first one VGA and second one is rom code and third draw image one is save of image rom display vga and get he problem , IEEE Std 1076-200812.4 Use clauses
TAG : vhdl
Date : October 05 2020, 01:00 AM , By : Nashid Shaila
What's the equivalent of Verilog tilde operator "~" in VHDL?
What's the equivalent of Verilog tilde operator "~" in VHDL?
it helps some times In Verilog and c-language, I can easy negate a vector by using the tilde operator. Example: , The not operator:
TAG : vhdl
Date : October 04 2020, 08:00 PM , By : Endang Djuana Tjhwa
Is "xor" bitwise or logical in VHDL?
Is "xor" bitwise or logical in VHDL?
this will help "logical" operators in Verilog (and C) are just an abbreviation resulting from the (mathematically incorrect) definition that anything nonzero is assumed "true" while a zero value is assumed "false". Such
TAG : vhdl
Date : October 04 2020, 08:00 PM , By : CMB
VHDL parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACK Process "Check Syntax"
VHDL parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACK Process "Check Syntax"
I wish this help you In VHDL when you want to access to a particular element of an array (std_logic_vector are array), you have to use () instead of [].
TAG : vhdl
Date : October 03 2020, 02:00 AM , By : chen kevin
How can we assign different signals to a single integer value?
How can we assign different signals to a single integer value?
should help you out I'm writing VHDL test bench for full adder , Yes you can - VHDL 2008 allows aggregate assignments.
TAG : vhdl
Date : October 02 2020, 05:00 PM , By : Raju Ravuri
How to find amplitude and frequency of an incoming sinusoidal signal (analog) in VHDL
How to find amplitude and frequency of an incoming sinusoidal signal (analog) in VHDL
seems to work fine The VHDL MAXIMUM function returns the maximum (ie larger) value of its two inputs. Your two inputs are input_sine and S_amp, which is always 0.0. So, Amp_out will equal input_sine when input_sine is positive and 0.0 when it is nega
TAG : vhdl
Date : September 28 2020, 07:00 PM , By : EntireFuton
How can i use floating point numbers in VHDL?
How can i use floating point numbers in VHDL?
hop of those help? you can this using integer multiplication.If you have a FPGA with 18 bit multipliers you multiply and then use the upper bits.
TAG : vhdl
Date : September 28 2020, 03:00 PM , By : Uwaiz Meghjani
maximum number of ports in a Verilog module or a VHDL entity
maximum number of ports in a Verilog module or a VHDL entity
wish help you to fix your issue The SystemVerilog LRM says, in 23.2.2 Port declarations
TAG : vhdl
Date : August 24 2020, 03:00 AM , By : ny1902
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